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product datasheet march 3, 2010 9.9-12.5gb/s optical modulator driver TGA4953-SL oc-192 metro and long haul applications surface mount package key features and performance ? metro msa compatible ? wide drive range (3v to 10v) ? single-ended input / output ? low power dissipation (1.1w at vo = 6v) ? very low rail ripple ? 25ps edge rates (20/80) ? small form factor - 11.4 x 8.9 x 2 mm - 0.450 x 0.350 x 0.080 inches primary applications description the triquint TGA4953-SL is part of a series of surface mount modulator drivers suitable for a variety of driver applications and is compatible with triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 1 primary applications ? mach-zehnder modulator driver for metro and long haul ? irz & duobinary applications variety of driver applications and is compatible with metro msa standards. the TGA4953-SL consists of two high performance wideband amplifiers combined with off chip circuitry assembled in a surface mount package. a single TGA4953-SL placed between the mux and optical modulator provides oems with a board level modulator driver surface mount solution. the TGA4953-SL provides metro and long haul designers with system critical features such as: low power dissipation (1.1w at vo = 6v), very low rail ripple, high voltage drive capability at 5v bias (6 v amplitude adjustable to 3 v), low output jitter (1ps rms typical), and low input drive sensitivity (250mv at vo = 6v). the TGA4953-SL requires external dc blocks, a low frequency choke, and control circuitry. the TGA4953-SL is available on an evaluation board. rohs compliant. TGA4953-SL evaluation board (metro msa conditions) 10.7 gb/s, vdd = 5 v, idd = 210 ma, (pdc = 1.1w) v out = 6 v pp , cpc = 50%, v in = 500 mv pp scale: 2 v/div, 15 ps/div measured performance
product datasheet march 3, 2010 TGA4953-SL table i maximum ratings symbol parameter value notes v d1 v d2t drain voltage 8 v 1 / 2 / v g1 v g2 gate voltage range -3v to 0v 1 / v ctrl1 v ctrl2 control voltage range -3v to v d 1 / i d1 i d2t drain supply current (quiescent) 200 ma 350 ma 1 / 2 / | i g1 | | i g2 | gate supply current 15 ma 1 / | i ctrl1 | | i ctrl2 | control supply current 15 ma 1 / 5 / p in input continuous wave power 23 dbm 1 / 2 / v in 12.5gb/s prbs input voltage 4 v pp 1 / 2 / p d power dissipation 4 w 1 / 2 / 3 / t ch operating channel temperature 150 0 c 4 / t mounting temperature 230 0 c triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 2 t m mounting temperature (10 seconds) 230 0 c t stg storage temperature -65 to 150 0 c 1 / these ratings represent the maximum operable val ues for this device 2 / combinations of supply voltage, supply current, i nput power, and output power shall not exceed p d at a package base temperature of 80 c 3 / when operated at this bias condition with a base plate temperature of 80 c, the mttf is reduced 4 / junction operating temperature will directly aff ect the device median time to failure (mttf). for maximum life, it is recommended that j unction temperatures be maintained at the lowest possible levels. 5 / assure v ctrl1 never exceeds v d1 , and v ctrl2 never exceeds v d2t during bias up and down sequences.
product datasheet march 3, 2010 table ii thermal information parameter test conditions t ch ( c) r ? jc ( c/w) mttf (hrs) r jc thermal resistance (channel to backside of package) v d2t = 4.7v i d2t = 150ma p diss = 0.71w t base = 80 c 98 26 >1e6 note: thermal transfer is conducted through the bot tom of the TGA4953-SL package into the motherboard. the motherboard must be designed to assure adequate thermal transfer to the base plate. TGA4953-SL triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 3
product datasheet march 3, 2010 table iii rf characterization table (t a = 25 c, nominal) parameter test conditions min typ max units notes small signal bandwidth 8 ghz saturated power bandwidth 12 ghz small signal gain 0.1, 2, 4 ghz 6 ghz 10 ghz 14 ghz 16 ghz 30 28 26 19 14 db 1 / 2 / input return loss 0.1, 2, 4, 6, 10, 14, 16 ghz 10 15 db 1 / 2 / TGA4953-SL triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 4 output return loss 0.1, 2, 4, 6, 10, 14, 16 ghz 10 15 db 1 / 2 / noise figure 3 ghz 2.5 db small signal agc range midband 30 db saturated output power 2, 4, 6, 8 & 10 ghz 25 dbm 6 / 7 /
product datasheet march 3, 2010 table iii rf characterization table (t a = 25 c, nominal) parameter test conditions min typ max units notes eye amplitude v d2t = 8.0v v d2t = 6.5v v d2t = 5.5v v d2t = 4.5v v d2t = 4.0v 10 8.0 7.0 6.0 5.5 v pp 3 / 4 / additive jitter (rms) v in = 500mv pp v in = 800mv pp 0.9 1.0 2.0 2.0 ps 5 / q-factor v in = 500mv pp v in = 800mv pp 28.5 28.5 35 35 v/v delta eye amplitude | 500?800 mv in p-p| -0.10 0.10 v pp delta crossing percentage | 500?800 mv in p-p| -6 6 % TGA4953-SL triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 5 table iii notes: 1 / verified at package level rf test 2 / typical package rf test bias conditions: vdd = 5v, adju st v g1 to achieve idd = 65ma then adjust v g2 to achieve i d2t = 115 ? 155 ma (idd = 180 - 220ma), v ctrl1 = -0.2v & v ctrl2 = +0.2 v 3 / verified by design, smt assembled onto a demonstration board detailed on sheet 6. 4 / v in = 250mv, data rate = 10.7gb/s, v d1 = v d2t or greater, v ctrl2 and v g2 are adjusted for maximum output. typical final idd under drive ~ 220 ma. 5 / computed using rss method where j rms_dut = (j rms_total 2 - j rms_source 2 ) 6 / verified at die level on-wafer probe 7 / power bias die probe: v tee = 8v, adjust v g to achieve idd = 175ma 5%, v ctrl = +1.5v note: at the die level, drain bias is applied through the rf output port using a bias tee, voltage is at the dc input to the bias tee
product datasheet march 3, 2010 demonstration board dc block mother board dc block rfout rfin TGA4953-SL triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 6 note: devices designated as epu are typically early in their characterization process prior to finaliz ing all electrical and process specifications. specifications are subject to chang e without notice. TGA4953-SL driver package
product datasheet march 3, 2010 demonstration board application circuit TGA4953-SL TGA4953-SL triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 7 notes: 1. c3 and c4 extend low frequency performance thru 30 khz. for applications requiring low frequency performance thru 100 khz, c3 and c4 may be omitted 2. c5 is a power supply decoupling capacitor and may be omitted 3. c6 and c7 are power supply decoupling capacitors and may be omitted when driven directly with an op-amp. impedance looking in to vctrl1 and vctrl2 is 10k real
product datasheet march 3, 2010 designator description manufacturer part number c1, c2 dc block, broadband presidio bb0502x7r104m16 vnt9820 c3, c4, c5 10uf capacitor mlc ceramic avx 0805yc106 ka c6, c7 0.01 ufcapacitor mlc ceramic avx 0603yc103ka c8 10 uf capacitor tantalum avx tajt106k016 l1 220 uh inductor panasonic or belfuse ellctv221m s581-4000-14 l2 330 nh inductor panasonic elj-far33mf2 r1, r2 274 resistor panasonic erj2rkd274 recommended components: demonstration board application circuit (continued) TGA4953-SL triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 8
product datasheet march 3, 2010 TGA4953-SL typical performance data is measured in a test fixture vdd idd rf(in) rf(out) TGA4953-SL driver id1 id2t TGA4953-SL triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 9 test fixture block diagram vg1 vctrl2 vg2 vctrl1
product datasheet march 3, 2010 typical measured performance on demonstration board 10.7gb/s 2^31-1, vdd=5v cpc=50% vo=6v vo=5v vo=4v vo=3v TGA4953-SL triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 10 input signal vin=500mv
product datasheet march 3, 2010 typical measured performance on demonstration board irz 2^31-1, vdd=8v vin=800mvpp 9.953gbps 10.7gbps 11.3gbps TGA4953-SL triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 11 input signal 10.7gbps
product datasheet march 3, 2010 typical bias conditions vdd=5v vo(v) 65 4 3 vg1(v) -0.66 -0.66 -0.66 -0.66 vg2(v) -0.57 -0.59 -0.67 -0.74 idd 221 198 172 147 vctrl2 +0.22 +0.04 -0.14 -0.34 TGA4953-SL triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 12 notes: 1. vdd=5v, id1=65ma, and vctrl1=-0.2v 2. vin=500mvpp 3. 50%cpc 4. actual bias points may be different. general comments for production operation of tga495 3-sl: 1. due to natural variations in gate voltages observ ed with gaas fet amplifiers used internally to the TGA4953-SL, optimal eye performance is obtained when the gate voltages (vg1 and vg2) are set to control desired drain currents (id1 and id2t) 2. vc2 feedback circuit recommended for output ampli tude correction.
product datasheet march 3, 2010 bias on 1. disable the output of the ppg 2. set vdd=0v vctrl1=0v vctrl2=0 vg1=0v and vg2=0v 3. set vg1=-1.5v vg2=-1.5v vctrl1=-0.2v 4. increase vdd to 5v observing idd. - assure idd=0ma 5. set vctrl2=+0.2v - idd should still be 0ma 6. make vg1 more positive until idd=65ma . - this is id1 (current into the first stage) - typical value for vg1 is -0.65v 7. make vg2 more positive until idd=180 ? 220 ma. - this sets id2t to 115 - 155 ma. bias off 1. disable the output of the ppg 2. set vctrl2=0v 3. set vdd=0v 4. set vctrl1=0v 5. set vg2=0v 6. set vg1=0v demonstration board - bias on/off procedure vdd=5v, vo=6vamp, cpc=50% (hot pluggable) TGA4953-SL triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 13 - this sets id2t to 115 - 155 ma. - typical value for vg2 is -0.55v 8. enable the output of the ppg. - set vin=500mv 9. output swing adjust : adjust vctrl2 slightly positive to increase output swing or adjus t vctrl slightly negative to decrease the output swin g. - typical value for vctrl2 is +0.22v for vo=6v. 10. crossover adjust : adjust vg2 slightly positive to push the crossover down or adj ust vg2 slightly negative to push the crossover up. - typical value for vg2 is -0.57v to center crossover with vo=6v.
product datasheet march 3, 2010 bias on 1. disable the output of mux 2. apply vg1, vg2, vctrl1, vctrl2, and vdd in any s equence. note: if vdd is applied first idd could reach near 400ma. 3. make vg1 more positive until idd=65ma . - this is id1 (current into the first stage) - typical value for vg1 is -0.65v 4. make vg2 more positive until idd=180 - 220ma. bias off remove vg1, vg2, vctrl1, vctrl2, and vdd in any sequence. production - initial alignment - bias procedure vdd=5v, vo=6vamp, cpc=50% (hot pluggable) bias network initial conditions - vg1=-1.5v vg2=-1.5v vctrl1=-0.2v vctrl2=+.1v vdd=5v TGA4953-SL triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 14 4. make vg2 more positive until idd=180 - 220ma. - this sets id2t to 115 - 155 ma. - typical value for vg2 is -0.55v 5. enable the output of the mux. - set vin=500mv 6. output swing adjust : adjust vctrl2 slightly positive to increase output swing or adjus t vctrl2 slightly negative to decrease the output swi ng. - typical value for vctrl2 is +0.22v for vo=6v. 7. crossover adjust : adjust vg2 slightly positive to push the crossover down or adj ust vg2 slightly negative to push the crossover up. - typical value for vg2 is -0.57v to center crossover with vo=6v.
product datasheet march 3, 2010 bias on 1. mux output can be either enabled or disabled 2. apply vg1, vg2, vctrl1, vctrl2, and vdd in any s equence. note: if vdd is applied first idd could reach near 400ma. 3. enable the output of the mux 4. output swing adjust : adjust vctrl2 slightly positive to increase output swing or adjus t vctrl slightly negative to decrease the output swin g. 5. crossover adjust : adjust vg2 slightly positive to push the crossover down or adj ust production - post alignment - bias procedure vdd=5v, vo=6vamp, cpc=50% (hot pluggable) bias network initial conditions - vg1= as found during initial alignment vg2=-as found during initial alignment vctrl1=-0.2v vctrl2=as found during initial alignment vdd=5v TGA4953-SL triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 15 5. crossover adjust : adjust vg2 slightly positive to push the crossover down or adj ust vg2 slightly negative to push the crossover up. bias off remove vg1, vg2, vctrl1, vctrl2, and vdd in any sequence. general comments for production operation of tga495 3-sl: 1. due to natural variations in gate voltages observ ed with gaas fet amplifiers used internally to the TGA4953-SL, optimal eye performance is obtained when the gate voltages (vg1 and vg2) are set to control desired drain currents (id1 and id2t) 2. vc2 feedback circuit recommended for output ampli tude correction.
product datasheet march 3, 2010 bias on 1. disable the output of mux 2. apply vg1, vg2, vctrl1, vctrl2, and vdd in any s equence. note: if vdd is applied first idd could reach near 400ma. 3. make vg1 more positive until idd=80ma . - this is id1 (current into the first stage) - typical value for vg1 is -0.55v 4. enable the output of the mux. bias off remove vg1, vg2, vctrl1, vctrl2, and vdd in any sequence. production - initial alignment ? irz bias procedure vdd=8v, vo=6vamp (hot pluggable) bias network initial conditions - vg1=-1.5v vg2=-2.0v vctrl1=+1.0v vctrl2=+2.0v vdd=8v TGA4953-SL triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 16 4. enable the output of the mux. - set vin=800mv 5. crossover adjust : adjust vg2 slightly negative to push the crossover towards zer o level. 6. output swing adjust : adjust vctrl2 slightly positive to increase output swing or adjus t vctrl2 slightly negative to decrease the output swi ng. 7. duty cycle fine tune : adjust vctrl1 slightly negative to reduce duty cycle percentage. 8. readjust vctrl2 for proper output amplitude.
product datasheet march 3, 2010 mechanical drawing TGA4953-SL 0.080 ref. lid 0.000 0.017 0.047 0.228 0.087 0.127 0.167 0.207 0.327 0.367 0.407 0.412 0.438 0.450 0.000 0.024 0.175 0.175 0.327 0.350 9 17 16 15 14 13 12 11 10 7 6 8 26 25 4 5 20 22 21 19 27 3 2 1 24 23 18 orientation mark 0.163 0.363 0.378 0.304 0.247 0.178 0.113 0.096 0.255 0.254 0.254 0.074 0.224 0.126 0.068 0.118 0.268 0.318 0.402 triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 17 notes: 1. dimensions: inches. tolerance: length and width : +/-.003 inches. height +/-.006 inches. adjacent pad to pad spacing : +/- .0002 inches. pad size: +/- .001 inches. 2. surface mount interface: material: ro4003 (thickness=.008 inches), 1/2oz co pper (thickness=.0007 inches) plating finish: 100-350 microinches nickel underpl ate, with 5-10 microinches flash gold overplate. 3. note for pin 13: pin 13 can be soldered to the pcb but must be left electrically open. 0.080 ref. 0.020 sidewall lid 0.025 x 0.041 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.027 x 0.018 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 pin #1 pin #2 pin #3 pin #4 pin #5 pin #6 pin #7 pin #8 pin #9 pin #10 pin #11 pin #12 pin #13 pin #14 n/c n/c vg1 n/c n/c vg2 n/c n/c rf out n/c n/c vd2t n/c vctrl2 0.018 x 0.041 0.018 x 0.041 0.018 x 0.041 0.020 x 0.018 0.023 x 0.033 0.049 x 0.049 0.023 x 0.033 0.023 x 0.033 0.049 x 0.049 0.023 x 0.033 0.023 x 0.033 0.023 x 0.033 pin #15 pin #16 pin #17 pin #18 pin #19 pin #20 pin #21 pin #22 pin #23 pin #24 pin #25 pin #26 pin #27 vd1 n/c vctrl1 rf in gnd gnd gnd gnd gnd gnd gnd gnd gnd
product datasheet march 3, 2010 recommended surface mount package assembly proper esd precautions must be followed while handl ing packages. clean the board with acetone. rinse with alcohol. allow the circuit to fully dry. triquint recommends using a conductive solder paste for attachment. follow solder paste and reflow ove n vendors? recommendations when developing a solder r eflow profile. typical solder reflow profiles are listed in the table below. hand soldering is not recommended. solder paste ca n be applied using a stencil printer or dot placeme nt. the volume of solder paste depends on pcb and compo nent layout and should be well controlled to ensure consistent mechanical and electrical perform ance. this package has little tendency to self-align during reflow . triquint recommends using no-clean solder for the t ga4953-sl. if cleaning is required, then de-ionized water or isopropyl alcohol solutions are acceptable . typical solder reflow profiles reflow profile snpb pb free ramp-up rate TGA4953-SL triquint semiconductor texas : (972)994-8465 fax (972)994-8504 web: www.triquint.com 18 gaas mmic devices are susceptible to damage from el ectrostatic discharge. proper precautions should be observed during handling, assembly and test. ramp-up rate 3 c/sec 3 c/sec activation time and temperature 60 ? 120 sec @ 140 ? 160 c 60 ? 180 sec @ 150 ? 200 c time above melting point 60 ? 150 sec 60 ? 150 sec max peak temperature 240 c 260 c time within 5 c of peak temperature 10 ? 20 sec 10 ? 20 sec ramp-down rate 4 ? 6 c/sec 4 ? 6 c/sec ordering information part package style TGA4953-SL land grid array surface mount (rohs comp liant) environmental ratings moisture sensitivity rating esd rating msl5a 1a

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